(1) Field of the Invention
The Invention relates to a non-volatile memory device, and more particularly, to a MONOS memory storage device.
(2) Description of the Related Art
MONOS (metal oxide nitride oxide silicon) device provides many advantages when implemented as a non-volatile memory element. It has good potential to achieve low voltage, high speed, and high density.
Eitan provides a double bit memory device using a MONOS stack layer, called NROM, in U.S. Pat. No. 5,966,603, as shown in FIG. 1. The gate oxide of a conventional NMOS device is simply replaced by a composite layer 12 of ONO (Oxide-Nitride-Oxide). The nitride layer 14 in the middle of the stack stores memory charge. Channel hot electrons are injected into the nitride storage region 16 over the drain side P-N junction. Since drain and source are symmetrical and convertible, the device can have two separate storage nodes in a nitride layer over each of the two P-N junctions, thus a single device can have two bits of memory in a unit cell. This NROM structure has some issues and challenges. The first issue is the shift up of threshold voltage (Vt) with program-erase cycling. Channel hot electrons are mostly injected at the edge of the channel, but a few electrons may also find their way to the center of the channel. Electrons stored over the middle of the channel are difficult to be neutralized by the hot hole injection erase operation and, thus, accumulate during repeated program-erase cycles. Another issue is read disturb. The voltage conditions for read are reversed from the voltage direction for program in that the source and drain are switched. During a normal read operation, the unselected bit in the unit cell may become lightly programmed, which leads to a Vt shift up on the unselected side over time.
Odanaka et al teach a Twin MONOS structure, as shown in FIG. 2, in U.S. Pat. No. 6,051,860. This structure has no nitride layer over the middle of a channel. Two memory gates 20 having underlying nitride storage 16 and a MOS gate 22 in between are placed over the channel. The middle MOS gate 22 works as a select gate. Since the middle gate has no nitride layer, no electrons or holes are injected or ejected. This channel profile is convenient for low voltage and fast program or erase. However, read disturb can occur due to injection of electrons into the unselected memory side during read. Program speed can be compromised when the other unselected side is programmed since program current is reduced.
Another issue is punch through due to short channel at read mode. While a channel length of FIG. 1 is that of a conventional n-MOS, a higher voltage than the n-MOS is applied to the drain in order to extend the depletion region under the storage on the drain side. Its effective channel becomes considerably shorter than n-MOS. The unselected gate in FIG. 2 is overridden by applying a high voltage, where the depletion region is extended under the select gate channel. Its effective channel length also becomes shorter than n-MOS. It is getting difficult to squeeze in a channel length of a CMOS device. It is more difficult for the two prior arts to squeeze their cell size.
U.S. Patent Application 2008/0057647 to Ho et al discloses forming a SONOS select gate in the bottom of a trench and a memory transistor with ONO in the upper portion of the trench. This device uses a conventional planar select transistor in series with a trench ONO device. It is geared more towards an integrated process which provides a low voltage cell operation compared to conventional floating gate devices.
U.S. Patent Application 2007/0187746 to Kashimura shows a vertical memory cell within a trench where the control gate is at the bottom of the trench and the word gate is at the top of the trench. In this device structure, the source and drain diffusions are both either at the very bottom of the trench in one embodiment, or both at the top of the mesa (i.e. along the surface of the substrate) in another embodiment. A pair of memory cells share a U-shaped channel. Its profile is symmetric. It would help issues for punch through and miniaturization, but not issues for read disturb and program speed when the other side cell is programmed, which prevent the pair from working as a dual bit.
U.S. Pat. No. 5,229,312 to Mukherjee et at shows a memory cell formed in a trench with ONO between the bottom and top gates. However, charge is stored in a floating gate, not in the nitride of the ONO layer. The ONO acts as an inter-gate dielectric, not as a memory layer.
U.S. Pat. No. 4,774,556 to Fujii et al has device separated into top and bottom diffusions, but the deposition of nitride is asymmetrical.